PIC17C756A-16/L Microchip Technology, PIC17C756A-16/L Datasheet - Page 170
![IC MCU OTP 16KX16 A/D PWM 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-16/L
Manufacturer Part Number
PIC17C756A-16/L
Description
IC MCU OTP 16KX16 A/D PWM 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-16/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
50
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Controller Family/series
PIC17
No. Of I/o's
50
Ram Memory Size
902Byte
Cpu Speed
16MHz
No. Of Timers
4
Package
68PLCC
Device Core
PIC
Family Name
PIC17
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
50
Interface Type
I2C/SPI/USART
On-chip Adc
12-chx10-bit
Number Of Timers
4
Processor Series
PIC17C
Core
PIC
Data Ram Size
902 B
Maximum Clock Frequency
33 MHz
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-16/L
Manufacturer:
MICROCHIP
Quantity:
101
Company:
Part Number:
PIC17C756A-16/L
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
- Current page: 170 of 304
- Download datasheet (6Mb)
PIC17C7XX
15.2.18
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA, by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted and
the SSPBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I
tion by asserting a START condition.
FIGURE 15-34:
DS30289B-page 170
SDA
SCL
BCLIF
2
2
C port to its IDLE state (Figure 15-34).
C bus is free, the user can resume communica-
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0.
SDA released
by master.
SDA line pulled low
by another source.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine,
and if the I
nication by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the
I
STAT register, or the bus is idle and the S and P bits
are cleared.
2
C bus can be taken when the P bit is set in the SSP-
2
C bus is free, the user can resume commu-
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2000 Microchip Technology Inc.
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