PIC16C558/JW Microchip Technology, PIC16C558/JW Datasheet - Page 18

• Manufacturer Part Number: PIC16C558/JW
• Description: IC MCU EPROM 2KX14 18CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C558/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-CDIP (0.300", 7.62mm) Window
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC16C55X
TABLE 4-1:
DS40143D-page 16
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh-1Eh
1Fh
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-9Eh
9Fh
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
Address
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.
4: PIC16C557 only.
shaded = unimplemented
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PCON
Name
—
—
—
—
—
—
—
—
—
—
—
(4)
SPECIAL REGISTERS FOR THE PIC16C55X
(4)
Addressing this location uses contents of FSR to address data memory (not a
physical register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a
physical register)
Program Counter's (PC) Least Significant Byte
TRISC7 TRISC6
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TRISB7
RBPU
IRP
Bit 7
RB7
RC7
GIE
GIE
—
—
—
—
—
—
(2)
INTEDG
TRISB6
RP1
Bit 6
RC6
RB6
(3)
(3)
—
—
—
—
—
—
(2)
Indirect data memory address pointer
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
T0CS
Bit 5
T0IE
T0IE
RP0
RB5
RC5
RP0
—
—
—
—
—
Preliminary
Write buffer for upper 5 bits of program counter ---0 0000
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111
Write buffer for upper 5 bits of program counter ---0 0000
T0SE
INTE
INTE
Bit 4
RA4
RC4
RB4
TO
TO
—
RBIE
RBIE
Bit 3
RC3
PSA
RA3
RB3
PD
PD
—
Bit 2
RC2
T0IF
T0IF
RA2
RB2
PS2
—
Z
Z
Bit 1
INTF
INTF
POR
RC1
RA1
RB1
PS1
DC
DC
 2002 Microchip Technology Inc.
Bit 0
RBIF
RBIF
RA0
RB0
RC0
PS0
—
C
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
0000 000x
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
0000 000x
---- --0-
POR Reset
Value on
—
—
—
—
—
—
—
—
—
—
—
Detail on
Page:
21
47
21
17
21
23
25
27
21
19
21
18
21
17
21
23
25
27
21
19
20
—
—
—
—
—
—
—
—
—
—
—