PIC17C762-16/L Microchip Technology, PIC17C762-16/L Datasheet - Page 214

• Manufacturer Part Number: PIC17C762-16/L
• Description: IC MCU OTP 8KX16 A/D 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C762-16/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 66
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Controller Family/series: PIC17
• No. Of I/o's: 66
• Ram Memory Size: 678Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL841 - DEVICE ADAPTER FOR PIC17C762DM173001 - KIT DEVELOPMENT PICDEM17AC164027 - ADAPTER PICSTART PLUS 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30289B-page 214
Before Instruction
After Instruction
operation
Decode
REG
REG
If REG
If REG
Q1
Q1
No
PC =
PC =
=
=
=
=
register ’f’
operation
Increment f, skip if not 0
[label]
0
d
(f) + 1
skip if not 0
None
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed in
WREG. If ’d’ is 1, the result is placed
back in register ’f’.
If the result is not 0, the next instruction,
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
1
1(2)
HERE
ZERO
NZERO
Read
0010
Q2
Q2
No
REG
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
f
[0,1]
255
INFSNZ f,d
(dest),
INFSNZ
010d
operation
Process
Data
Q3
Q3
No
REG, 1
ffff
destination
operation
Write to
Q4
Q4
No
ffff
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
=
=
Inclusive OR Literal with WREG
[ label ]
0
(WREG) .OR. (k)
Z
The contents of WREG are OR’ed with
the eight-bit literal 'k'. The result is
placed in WREG.
1
1
IORLW
literal 'k'
Read
1011
Q2
0x9A
0xBF
k
2000 Microchip Technology Inc.
255
IORLW k
0011
0x35
Process
Data
Q3
kkkk
(WREG)
Write to
WREG
Q4
kkkk