ATMEGA2560-16CU Atmel, ATMEGA2560-16CU Datasheet - Page 31

• Manufacturer Part Number: ATMEGA2560-16CU
• Description: IC MCU AVR 256K FLASH 100-CBGA
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560-16CU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Operating Supply Voltage: 4.5 V to 5.5 V
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
Figure 8-3.
Note:
Figure 8-4.
Note:
System Clock (CLK
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal
or external).
External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
DA7:0
A15:8
CPU
ALE
WR
RD
DA7:0
A15:8
CPU
ALE
)
WR
RD
Prev. addr.
Prev. data
Prev. data
Prev. data
)
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
ATmega640/1280/1281/2560/2561
T1
Address
Address
Address
T2
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
Address
T3
Data
Data
Data
T4
XXXXXXXX
T4
T5
(1)
(1)
31