ADUC812BSZ Analog Devices Inc, ADUC812BSZ Datasheet - Page 44

• Manufacturer Part Number: ADUC812BSZ
• Description: IC ADC 12BIT MULTICH MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC812BSZ

• Core Size: 8-Bit
• Program Memory Size: 8KB (8K x 8)
• Core Processor: 8052
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Eeprom Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 1.3MIPS
• No. Of Timers: 3
• Package: 52MQFP
• Device Core: 8052
• Family Name: ADuC8xx
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: I2C/SPI/TWI/UART
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC812
OTHER HARDWARE CONSIDERATIONS
To facilitate in-circuit programming, plus in-circuit debug and
emulation options, users will want to implement some simple
connection points in their hardware that will allow easy access
to download, debug, and emulation modes.
In-Circuit Serial Download Access
Nearly all ADuC812 designs will want to take advantage of the
in-circuit reprogrammability of the chip. This is accomplished by
a connection to the ADuC812’s UART, which requires an external
RS-232 chip for level translation if downloading code from a PC.
Basic configuration of an RS-232 connection is illustrated in
Figure 46 with a simple ADM202 based circuit. If users would
rather not design an RS-232 chip onto a board, refer to the Appli-
cation Note, uC006–A 4-Wire UART-to-PC Interface, (available
at www.analog.com/microconverter) for a simple (and zero-cost-
per-board) method of gaining in-circuit serial download access
to the ADuC812.
In addition to the basic UART connections, users will also need
a way to trigger the chip into download mode. This is accom-
plished via a 1 k pull-down resistor that can be jumpered onto
the PSEN pin, as shown in Figure 46. To get the ADuC812
ANALOG INPUT
V
DAC OUTPUT
REF
OUTPUT
DV
DD
V
CC
ADM810
GND
51
AV
C1+
V+
C1–
C2+
C2–
V–
T2OUT
R2IN
RST
DD
Figure 46. Typical System Configuration
ADM202
R1OUT
R2OUT
T1OUT
GND
R1IN
T1IN
T2IN
V
CC
ADC0
AV
AGND
C REF
V REF
DAC0
DAC1
52
DD
DV
51
DD
50
–44–
49
DV
48
into download mode, simply connect this jumper and power-
cycle the device (or manually reset the device, if a manual reset
button is available) and it will be ready to receive a new program
serially. With the jumper removed, the device will come up in
normal mode (and run the program) whenever power is cycled
or RESET is toggled.
Note that PSEN is normally an output (as described in the External
Memory Interface section), and is sampled as an input only on
the falling edge of RESET (i.e., at power-up or upon an external
manual reset). Note also that if any external circuitry uninten-
tionally pulls PSEN low during power-up or reset events, it could
cause the chip to enter download mode and therefore fail to begin
user code execution as it should. To prevent this, ensure that no
external signals are capable of pulling the PSEN pin low, except
for the external PSEN jumper itself.
Embedded Serial Port Debugger
From a hardware perspective, entry to serial port debug mode is
identical to the serial download entry sequence described above.
In fact, both serial download and serial port debug modes can be
thought of as essentially one mode of operation used in two
different ways.
DD
DV
ADuC812
47
DD
9-PIN D-SUB
46
FEMALE
45
DOWNLOAD/DEBUG
(NORMALLY OPEN)
1
2
3
4
5
6
7
8
9
44 43
ENABLE JUMPER
1k
42
NOT CONNECTED IN THIS EXAMPLE
41
XTAL2
XTAL1
DGND
DV
40
1k
DD
DV
38
37
36
34
27
39
35
33
32
31
30
29
28
DD
11.0592MHz
DV
DD
2-PIN HEADER FOR
EMULATION ACCESS
(NORMALLY OPEN)
REV. E