EP7311-IV Cirrus Logic Inc, EP7311-IV Datasheet - Page 44

• Manufacturer Part Number: EP7311-IV
• Description: IC ARM720T MCU 74MHZ 208-LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7311-IV

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 74MHz
• Connectivity: Codec, EBI/EMI, IrDA, Keypad, Multimedia Codec, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1230

EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
256-Ball PBGA Pinout (Top View)
44
M nTEST[0]
A
B
C
D
E
G
H
K LEDDRV
N nEXTFIQ
P VSSRTC
R
F
J
L
T VDDRTC
Y20
Ball Location
nSDRAS
WRITE/
RXD[2]
RXD[1]
VDDIO
nCS[5]
VDDIO
RTCIN
PB[5]
PB[1]
PA[7]
PA[3]
*
†
‡ Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
“With p/u” means with internal pull-up of 100 KOhms on the pin.
1
Strength 2 = 12 ma
Strength 1 = 4 ma
Note:
BOOTSEL[1]
EXPRDY
RTCOUT
SDQM[1]
EXPCLK
nEINT[2]
nCS[4]
VDDIO
VDDIO
PHDIN
VDDIO
PE[1]/
PD[7]/
PB[7]
PB[3]
PA[5]
PA[1]
DSR
2
1) For pin locations see
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information.
VDDIO
SDQM[0]
VDDIO
VDDIO
nCS[1]
nCS[3]
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
PD[6]/
PD[4]
TDO
TDI
Name
3
Table 21. 204-Ball TFBGA Ball Listing (Continued)
BOOTSEL[0]
nSDCAS
nEINT[1]
SDCLK
VDDIO
VDDIO
WORD
VDDIO
nMOE/
TXD[2]
VSSIO
PE[0]/
PB[4]
PA[4]
PA[2]
PD[1]
PD[3]
DCD
4
nTEST[1]
SSITXDA
SDQM[3]
CLKSEL
SSICLK
Table
CLKEN
VDDIO
VDDIO
VSSIO
nCS[2]
VSSIO
PE[2]/
PD[5]
Strength
RUN/
PB[6]
PA[6]
PA[0]
TMS
5
V.
†
nSDCS[1]
SSIRXFR VDDCORE DRIVE[0]
VSSRTC
VSSRTC
nADCCS
nSDWE
EINT[3]
nMWE/
VDDIO
VSSIO
nCS[0]
VSSIO
TXD[1]
VSSIO
DD[1]
PB[0]
PD[2]
6
©
Figure 18. 256-Ball PBGA Package
Copyright Cirrus Logic, Inc. 2005
nSDCS[0]
LEDFLSH
SSITXFR
SSIRXDA
SDQM[2]
VSSRTC
VSSRTC
SDCKE
VDDIO
VSSIO
VSSIO
PD[0]/
DD[2]
PB[2]
CTS
M
7
(All Rights Reserved)
Reset
State
ADCOUT
VSSRTC
VSSRTC
VSSRTC
DRIVE[1]
ADCCLK
VDDIO
VDDIO
ADCIN
VDDIO
CL[1]
CL[2]
DD[3]
DD[0]
FRM
8
VDDCORE
VSSRTC
VSSRTC
VSSRTC
SMPCLK
VSSIO
COL[4]
COL[6]
VSSIO
COL[7]
FB[0]
FB[1]
D[0]
D[3]
A[0]
A[1]
Pad power
9
Type
VSSRTC
DRA[10]
VSSIO
COL[0]
COL[2]
VDDIO
COL[3]
COL[5]
A[17]/
TCLK
A[10]
D[31]
D[2]
D[1]
D[4]
D[5]
D[6]
10
Digital I/O power,
3.3V
VSSOSC
nPWRFL
VSSRTC
VSSRTC
DRA[11]
VSSIO
COL[1]
VDDIO
VSSIO
A[16]/
A[11]
D[20]
D[27]
D[29]
A[3]
A[2]
A[7]
Description
11
MOSCIN
DRA[12]
VDDIO
VDDIO
BATOK
DRA[5]
VSSIO
VSSIO
VSSIO
A[15]/
A[22]/
A[12]
D[19]
D[26]
D[30]
BUZ
A[4]
A[8]
12
HALFWORD
nMEDCHG/
nBATCHG
DRA[14]
DRA[13]
nBROM
VDDIO
DRA[6]
DRA[4]
VDDIO
DRA[0]
VSSIO
A[13]/
A[14]/
A[21]/
A[23]/
A[27]/
D[18]
D[28]
A[6]
A[5]
A[9]
13
MOSCOUT VDDOSC
WAKEUP
VSSIO
VDDIO
nTRST
VDDIO
DRA[2]
DRA[1]
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
A[25]/
A[26]/
14
VDDIO
VDDIO
DRA[9]
DRA[7]
VDDIO
nPOR
A[18]/
A[20]/
D[11]
D[12]
D[14]
D[16]
D[22]
D[24]
D[25]
D[7]
D[9]
15
DS506F1
nEXTPWR C
nURESET B
VDDIO
VDDIO
DRA[8]
VDDIO
DRA[3]
VSSIO
VSSIO
A[19]/
A[24]\
D[10]
D[13]
D[15]
D[17]
D[21]
D[23]
D[8]
16
D
G
H
M
N
R
A
E
F
K
L
P
T
J