EP7312-IR-90 Cirrus Logic Inc, EP7312-IR-90 Datasheet - Page 6

• Manufacturer Part Number: EP7312-IR-90
• Description: IC ARM720T MCU 90MHZ 204-TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7312-IR-90

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 204-TFBGA
• For Use With: 598-1209 - KIT DEVELOPMENT EP73XX ARM7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: 598-1244

EP7312
High-Performance, Low-Power System on Chip
Description of the EP7312’s Components, Functionality, and Interfaces
The following sections describe the EP7312 in more detail.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro
controller that controls a wide range of on-chip peripherals.
The processor utilizes a three-stage pipeline consisting of
fetch, decode and execute stages. Key features include:
•
•
•
•
Power Management
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
Table 1
MaverickKey
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
6
BATOK
nEXTPWR
nPWRFL
nBATCHG
ARM (32-bit) and Thumb (16-bit compressed) instruction
sets
Enhanced MMU for Microsoft Windows CE and other
operating systems
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated Entries
Pin Mnemonic
• Operating — This state is the full performance state.
• Idle — This state is the same as the Operating State,
• Standby — This state is equivalent to the computer
shows the power management pin assignments.
Table 1. Power Management Pin Assignments
All the clocks and peripheral logic are enabled.
except the CPU clock is halted while waiting for an
event such as a key press.
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.
™
Unique ID
I/O
I
I
I
I
Battery ok input
External power supply sense
input
Power fail sense input
Battery changed sense input
Pin Description
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7312 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7312 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.
Memory Interfaces
There are two main external memory interfaces. The first one
is
programmable wait-state timings and includes burst-mode
capability, with six chip selects decoding six 256 MB sections
of addressable space. For maximum flexibility, each bank can
be specified to be 8-, 16-, or 32-bits wide. This allows the use
of 8-bit-wide boot ROM options to minimize overall system
cost. The on-chip boot ROM can be used in product
manufacturing to serially download system code into system
FLASH memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density. shows the Static Memory Interface pin
assignments.
nCS[5:0]
A[27:0]
D[31:0]
nMOE/nSDCAS
nMWE/nSDWE
HALFWORD
WORD
WRITE/nSDRAS
Note:
the
Pin Mnemonic
Table 2. Static Memory Interface Pin Assignments
ROM/SRAM/FLASH-style
Pins are multiplexed. See
more information.
(Note)
(Note)
(Note)
I/O
I/O
O
O
O
O
O
O
O
Table 19 on page 11
Chip select out
Address output
Data I/O
ROM expansion OP enable
ROM expansion write enable
Halfword access select
output
Word access select output
Transfer direction
Pin Description
interface
for
that
DS508F1
has