Z8F012APB020SG Zilog, Z8F012APB020SG Datasheet - Page 70

• Manufacturer Part Number: Z8F012APB020SG
• Description: IC ENCORE XP MCU FLASH 1K 8DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012APB020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4033; Z8F012APB020SG

PS022825-0908
Caution:
Caution:
Caution:
Caution:
Software Interrupt Assertion
Watchdog Timer Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the timeout
condition continues. As it operates on a different (and usually slower) clock domain than
the rest of the device, the Watchdog Timer continues to assert this interrupt for many
system clocks until the counter rolls over.
The following coding style that clears bits in the Interrupt Request registers is not
recommended. All incoming interrupts received between execution of the first
mand and the final LDX command are lost.
The following coding style used to generate software interrupts by setting bits in the
Interrupt Request registers is not recommended. All incoming interrupts received be-
tween execution of the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to set bits in the Interrupt
Request registers:
Interrupt Request 0 register:
To avoid missing interrupts, use the following coding style to clear bits in the
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
Z8 Encore! XP
Product Specification
®
Interrupt Controller
F082A Series
LDX
com-
59