STM8S105K4B6 STMicroelectronics, STM8S105K4B6 Datasheet - Page 119
STM8S105K4B6
Manufacturer Part Number
STM8S105K4B6
Description
MCU 8BIT 16K FLASH 32-SDIP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S105C4T6.pdf
(127 pages)
Specifications of STM8S105K4B6
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-SDIP (0.400", 10.16mm)
Processor Series
STM8S10x
Core
STM8
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
For Use With
497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
STM8S105xx
OPT3 watchdog
OPT4 wakeup
AFR5
(check only one option)
AFR6
(check only one option)
AFR7
(check only one option)
WWDG_HALT
(check only one option)
WWDG_HW
(check only one option)
IWDG_HW
(check only one option)
LSI_EN
(check only one option)
HSITRIM
(check only one option)
PRSC
(check only one option)
CKAWUSEL
(check only one option)
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
[ ] 1: Port D4 alternate function = BEEP.
DocID14771 Rev 10
[ ] for 16 MHz to 128 kHz prescaler.
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
[ ] 0: LSI clock source selected for AWU.
[ ] 1: HSE clock with prescaler selected as clock source
for AWU.
[ ] 0: No reset generated on halt if WWDG active.
[ ] 1: Reset generated on halt if WWDG active.
[ ] 0: WWDG activated by software.
[ ] 1: WWDG activated by hardware.
[ ] 0: IWDG activated by software.
[ ] 1: IWDG activated by hardware.
[ ] 0: LSI clock is not available as CPU clock source.
[ ] 1: LSI clock is available as CPU clock source.
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
Ordering information
119/127