ST7FLITE20F1B6 STMicroelectronics, ST7FLITE20F1B6 Datasheet - Page 83

• Manufacturer Part Number: ST7FLITE20F1B6
• Description: IC MCU 8BIT 8K FLASH 20-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE20F1B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE2x
• Core: ST7
• Data Bus Width: 8 bit
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5517 - EVAL BOARD 1PHASE ENERGY METER497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
EOC SPEED ADON
7
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
CH3
CH2
0
0
0
0
1
1
1
CH2
CH1
CH1
0
0
1
1
0
0
1
CH0
CH0
0
1
0
1
0
1
0
0
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. User is sug-
gested to use this bit to calibrate the ADC when
amplifier is ON. Setting this bit internally connects
amplifier input to 0v. Hence, corresponding ADC
output can be used in software to eliminate ampli-
fier-offset error.
0: Calibration off
1: Calibration on (The input voltage of the amp is
set to 0V)
Note: It is advised to use this bit to calibrate the
ADC when the amplifier is ON. Setting this bit in-
ternally connects the amplifier input to 0v. Hence,
the corresponding ADC output can be used in soft-
ware to eliminate an amplifier-offset error.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
This bit is set and cleared by software.
D9
7
7
0
D8
0
D7
f
f
0
f
CPU
CPU
f
ADC
CPU
/2
/4
AMP
CAL
D6
SLOW
D5
AMP-
SEL
D4
SLOW SPEED
ST7LITE2
0
0
1
D3
D1
83/133
D2
D0
0
1
x
0
0
1