ST72F63BH2T1 STMicroelectronics, ST72F63BH2T1 Datasheet - Page 116
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/12/15/121518/stmicroelectronics-48-lqfp_sml.jpg)
ST72F63BH2T1
Manufacturer Part Number
ST72F63BH2T1
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BH2T1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
48-LQFP
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
27
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST7MDTULS-EVAL, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F63BH2T1
Manufacturer:
STMicroelectronics
Quantity:
10 000
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On-chip peripherals
11.5.5
11.5.6
116/186
Low power modes
Table 41.
Interrupts
Figure 49. Event flags and interrupt generation
1. EVF can also be set by EV6 or an error from the SR2 register.
Table 42.
The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
Mode
WAIT
HALT
STOPF
(1)
BERR
ARLO
ADSL
No effect on I²C interface.
I²C interrupts cause the device to exit from Wait mode.
I²C registers are frozen.
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The
I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
BTF
SB
AF
Low power modes
Interrupts
Interrupt event
Doc ID 7516 Rev 8
ITE
Description
STOPF
ARLO
BERR
Event
ADSL
BTF
flag
SB
AF
control
Enable
ITE
bit
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST7263Bxx
from
Exit
Halt
No
No
No
No
No
No
No
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