ST7FLITE29F2M7TR STMicroelectronics, ST7FLITE29F2M7TR Datasheet - Page 44

• Manufacturer Part Number: ST7FLITE29F2M7TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE29F2M7TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE2x
• Core: ST7
• Data Bus Width: 8 bit
• Development Tools By Supplier: ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE2
POWER SAVING MODES (Cont’d)
Figure 30. AWUFH Mode Flow-chart
44/133
1
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
(Active-Halt disabled)
N
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
5)
ON
ON
ON
ON
10
4)
4)
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 5, “Interrupt
Mapping,” on page 35 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after an additional delay of t
Figure
12).
STARTUP
(see