ST7FMC1K4T6 STMicroelectronics, ST7FMC1K4T6 Datasheet - Page 214

• Manufacturer Part Number: ST7FMC1K4T6
• Description: MCU 8BIT 16K FLASH 32TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC1K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FMC1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4866

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Bits 2:0 = VR[2:0]: BEMF/demagnetisation Refer-
These bits select the Vref value as shown in the
Table
Demagnetisation detection.
Table 64. Threshold voltage setting
*Typical values for V
214/309
VR2
ence threshold
1
1
1
1
0
0
0
0
64. The Vref value is used for BEMF and
VR1
1
1
0
0
1
1
0
0
VR0
1
0
1
0
1
0
1
0
DD
Threshold voltage set by ex-
Vref voltage threshold
=5V
ternal MCVREF pin
3.5V*
2.5V*
1.5V*
0.6V*
0.2V*
2V*
1V*
PHASE STATE REGISTER (MPHST)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS[1:0]*: Input Selection bits
These bits mainly select the input to connect to
comparator as shown in
figuration (IS[1:0] = 11) specifies that an incremen-
tal encoder is used (in that case MCIA and MCIB
digital signals are directly connected to the incre-
mental encoder interface and the analog multi-
plexer is bypassed.
Table 65. Input Channel Selection
Bits 5:0 =OO[5:0]*: Channel On/Off bits
These bits are used to switch channels on/off at
the next C event if the DAC bit =0 or directly if
DAC=1
0: Channel Off, the relevant switch is OFF, no
1: Channel On the relevant switch is ON, PWM is
Table 66. OO[5:0] Bit Meaning
* Preload bits, new value taken into account at
next C event.
Caution: As the MPHST register contains bits with
preload, the whole register has to be written at
once. This means that a Bit Set or Bit Reset in-
struction on only one bit without preload will have
the effect of resetting all the bits with preload.
IS1*
IS1
PWM possible
possible (not signifiant when PCN or DTE bit is
set).
7
0
0
1
1
IS0*
6
IS0
OO[5:0]
0
1
0
1
0
1
OO5*
5
Both MCIA and MCIB: Encoder Mode
OO4*
4
Channel selected
Table
OO3*
3
Output Channel State
MCIA
MCIB
MCIC
65. The fourth con-
OO2*
2
Inactive
Active
OO1*
1
OO0*
0