ST62T60CB6 STMicroelectronics, ST62T60CB6 Datasheet - Page 29
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ST62T60CB6
Manufacturer Part Number
ST62T60CB6
Description
IC MCU 8BIT W/ADC 20-PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet
1.ST62T60CB6.pdf
(83 pages)
Specifications of ST62T60CB6
Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LED, LVD, POR, WDT
Number Of I /o
13
Program Memory Size
3.8KB (3.8K x 8)
Program Memory Type
OTP
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 8-bit
Controller Family/series
ST6
No. Of I/o's
13
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Quantity:
415
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Part Number:
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Quantity:
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ST6253C ST6263C ST6263B ST6260C ST6260B
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 20. Digital Watchdog Block Diagram
29/83
S
RSFF
RESET
Q
R
DB0
DB1.7
8
WRITE
DATA BUS
-2
LOAD
7
RESET
SET
Figure 19. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
SWITCH
SET
-2
8
OSCILLATOR
CLOCK
-12
VA00010
NMI
I/O
VR02002