ST72F623F2M1TR STMicroelectronics, ST72F623F2M1TR Datasheet - Page 45
ST72F623F2M1TR
Manufacturer Part Number
ST72F623F2M1TR
Description
IC MCU 8BIT 8K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F622L2M1.pdf
(139 pages)
Specifications of ST72F623F2M1TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 3 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to two Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 33. PWM Auto-reload Timer Function
AUTO-RELOAD
DUTY CYCLE
f
(PWMDCRx)
WITH OEx=1
AND OPx=0
PWM
REGISTER
REGISTER
WITH OEx=1
AND OPx=1
(ARTARR)
= f
COUNTER
255
000
/ (256 - ARTARR)
Doc ID 6996 Rev 5
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
The maximum available resolution for the PWMx
duty cycle is:
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
Resolution = 1 / (256 - ARTARR)
ST7262xxx
t
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