STM32F103T6U6A STMicroelectronics, STM32F103T6U6A Datasheet - Page 15
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STM32F103T6U6A
Manufacturer Part Number
STM32F103T6U6A
Description
MCU ARM 32BIT 32KB FLASH 36VFQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F103C4T6A.pdf
(87 pages)
Specifications of STM32F103T6U6A
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
26
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
36-VFQFN, 36-VFQFPN
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
10 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
26
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (12 bit, 10 Channel)
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F103T6U6A
Manufacturer:
ST
Quantity:
20
Company:
Part Number:
STM32F103T6U6A
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F103x4, STM32F103x6
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed
APB domain is 36 MHz. See
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
V
Provided externally through V
V
and PLL (minimum voltage to be applied to V
V
V
registers (through power switch) when V
DD
SSA
DDA
BAT
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
and V
DDA
SSA
= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
must be connected to V
Figure 2
Doc ID 15060 Rev 5
DD
pins.
for details on the clock tree.
DD
DD
and V
is not present.
DDA
SS
is 2.4 V when the ADC is used).
Figure 11: Power supply
, respectively.
Description
scheme.
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