ST72F321BAR6T6 STMicroelectronics, ST72F321BAR6T6 Datasheet - Page 185

• Manufacturer Part Number: ST72F321BAR6T6
• Description: MCU 8BIT 32KB FLASH/ROM 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321BAR6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5582

KNOWN LIMITATIONS (Cont’d)
15.1.4 SCI Wrong Break duration
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (f
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
15.1.5 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.6 TIMD set simultaneously with OC
interrupt
If the 16-bit timer is disabled at the same time the
output compare event occurs then output compare
flag gets locked and cannot be cleared before the
timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the
output compare flag cannot be cleared in the timer
interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly.
CPU
=8MHz and SCI-
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
Workaround
Disable the timer interrupt before disabling the tim-
er. Again while enabling, first enable the timer then
the timer interrupts.
Perform the following to disable the timer:
pare interrupt
Perform the following to enable the timer again:
er
interrupt
15.1.7 I2C Multimaster
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
15.1.8 Pull-up always active on PE2
The I/O port internal pull-up is always active on I/O
port E2. As a result, if PE2 is in output mode low
level, current consumption in Halt/Active Halt
mode is increased.
15.1.9 ADC accuracy 32K Flash devices
The ADC accuracy in 32K Flash Devices deviates
from table in
lows:
TACR1 or TBCR1 = 0x00h; // Disable the com-
TACSR | or TBCSR | = 0x40; // Disable the timer
TACSR & or TBCSR &= ~0x40; // Enable the tim-
TACR1 or TBCR1 = 0x40; // Enable the compare
Symbol
|E
|E
|E
|E
|E
O
G
D
T
L
|
|
|
|
|
section 12.12.3 on page 169
Max
4.5
6
5
2
3
Unit
LSB
185/187
as fol-