Z86E4312VSG Zilog, Z86E4312VSG Datasheet - Page 62

• Manufacturer Part Number: Z86E4312VSG
• Description: IC MICROCONTROLLER 4K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4312VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 236 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3978; Z86E4312VSG

PS022901-0508
Note:
Note:
Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A “1” in
this location brings the comparator outputs to P34 and P37, and a “0” releases the Port to
its standard I/O configuration. The default value is 0.
Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit
(D1=0) or configured as push-pull active by setting this bit (D1=1). The default value is 1.
Port 0 Open-Drain (D2). Port 0 can be configured as an open-drain by resetting this bit
(D2=0) or configured as push-pull active by setting this bit (D2=1). The default value is 1.
Low EMI Port 0 (D3). Port 0 can be configured as a Low EMI Port by resetting this bit
(D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1.
Low EMI Port 1 (D4). Port 1 can be configured as a Low EMI Port by resetting this bit
(D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1.
Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit
(D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1.
Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit
(D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1.
Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscilla-
tor. A “1” in this location configures the oscillator with standard drive. While a “0” config-
ures the oscillator with low noise drive, however, it does not affect the relationship of
SCLK and XTAL. The low EMI mode will reduce the drive of the oscillator (OSC). The
default value is 1.
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and
determines the mode of Stop Mode Recovery
bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP
Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is
required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3,
and 4 of the SMR register specify the Stop Mode Recovery Source. The SMR is located in
Bank F of the Expanded Register File at address 0BH.
The emulator does not support Port 1 low EMI mode and must be set
D4 = 1.
4 MHz is the maximum external clock frequency when running in the
low EMI oscillator mode.
(Figure
CMOS Z8
31). All bits are Write Only except
®
Product Specification
OTP Microcontrollers
Electrical Characteristics
58