STR750FV0H6 STMicroelectronics, STR750FV0H6 Datasheet - Page 62
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STR750FV0H6
Manufacturer Part Number
STR750FV0H6
Description
MCU 32BIT 64K FLASH 100-LFBGA
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet
1.STR750FV0T6.pdf
(84 pages)
Specifications of STR750FV0H6
Core Processor
ARM7
Core Size
32-Bit
Speed
60MHz
Connectivity
CAN, I²C, SPI, SSI, SSP, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
72
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
CAN, I2C, SPI, SSI, SSP, USB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
72
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5988 - BOARD DEVELOPMENT LOVE STR750497-5754 - KIT STARTER IAR STR750497-5753 - KIT STARTER KEIL FOR STR7/STR9497-5752 - KIT STARTER IAR FOR STR7/STR9497-5751 - KIT STARTER HITEX FOR STR750497-5748 - BOARD EVALUATION FOR STR750XF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR750FV0H6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical parameters
6.3.10
62/84
Communication interface characteristics
SSP synchronous serial peripheral in master mode (SPI or TI mode)
General operating conditions: V
Table 38.
1. Data based on characterisation results, not tested in production.
2. Max frequency for the 2 SSPs is f
t
Symbol
t
SCKNSSH
t
t
w(SCKH)
t
t
NSSLQV
w(SCKL)
t
t
limitation due to I/O speed capability. SSP0 uses IO4 type while SSP1 uses IO2 type I/Os.
SCKQV
SCKQX
r(SCK)
f(SCK)
f
SCK
t
t
su
h
SPI clock frequency
SPI clock rise time
SPI clock fall time
SCK high and low time
NSS low to Data Output
MOSI valid time
SCK last edge to NSS high
SCK trigger edge to data
output MOSI valid time
SCK trigger edge to data
output MOSI invalid time
Data input (MISO) setup
time w.r.t SCK sampling
edge
Data input (MISO) hold time
w.r.t SCK sampling edge
SSP master mode characteristics
Parameter
PCLK
(2)
33
, 3.0V to 3.3V, V18 =1.8V, C
/2; f
PCLK
CPHA = 0
CPHA = 1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
max = 32 MHz. This takes into account the frequency
Conditions
(1)
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
Min
L
25
25
0
0
0
0
≈
45 pF.
0.5t
0.5t
0.5t
0.5t
t
t
SCK
SCK
SCK
SCK
SCK
SCK
Max
16
14
33
11
30
19
30
15
30
+15ns
+30ns
8
+15ns
+30ns
+15ns
+30ns
Unit
MHz
ns