Z86E3116SSC Zilog, Z86E3116SSC Datasheet - Page 35

• Manufacturer Part Number: Z86E3116SSC
• Description: IC MICROCONTROLLER 2K 28-SOIC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E3116SSC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: OTP
• Ram Size: 125 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-1055

Zilog
DS97Z8X0502
Working Register
Group Pointer
U = Unknown
Notes:
†
*
**
For Z86E40 (ROMless) reset condition: "10110110"
Will not be reset with a STOP Mode Recovery
Will not be reset with a STOP Mode Recovery, except Bit D0.
%FO
%FF
%7F
%0F
%00
7
REGISTER POINTER
6
Z86E30/E40 Only
Z86E30/E40 Only
5
Z8 Reg. File
4
3
2
1
Figure 26. Expanded Register File Architecture
Expanded Register
0
Group Pointer
P R E L I M I N A R Y
Reserved
**
†
*
*
*
*
*
*
REGISTER
EXPANDED REG. GROUP (F)
REGISTER
EXPANDED REG. GROUP (0)
REGISTER
% F8
% FF
% FE
% FD
% FC
% FB
% FA
% F9
% F7
% F6
% F5
% F4
% F3
% F2
% F1
% F0
% (F) 0F
% (F) 0E
% (F) 0D
% (F) 0C
% (F) 0B
% (F) 0A
% (F) 09
% (F) 08
% (F) 07
% (F) 06
% (F) 05
% (F) 04
% (F) 03
% (F) 02
% (F) 01
% (F) 00
% (0) 03
% (0) 02
% (0) 01
% (0) 00
Z8
®
STANDARD CONTROL REGISTERS
SPL
SPH
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
WDTMR
Reserved
SMR2
Reserved
SMR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
P3
P2
P1
P0
Reserved
Z8 4K OTP Microcontroller
RESET CONDITION
RESET CONDITION
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
U
U
U
U
0
0
0
U
0
0
U
0
0
1
U
U
U
U
0
U
0
1
1
U
U
U
U
0
0
0
U
U
0
U
1
0
1
U
U
U
U
0
U
0
1
1
U
1
U
U
U
0
0
0
U
U
0
U
0
0
1
U
U
U
U
0
U
1
1
U
0
0
0
U
U
0
U
0
0
1
U
U
U
U
0
0
0
1
1
U
U
U
Z86E30/E31/E40
U
0
0
0
U
U
0
U
1
0
1
U
U
U
U
0
U
U
U
U
1
0
1
U
U
0
0
0
U
U
0
U
1
0
1
U
U
U
U
0
1
0
1
U
U
U
0
0
0
U
U
0
U
0
0
1
U
U
0
U
0
0
0
0
1
U
U
U
U
U
0
0
0
U
U
0
U
1
0
1
0
U
0
U
0
1
0
0
0
U
U
U
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