F272-BAG-T STMicroelectronics, F272-BAG-T Datasheet - Page 170

• Manufacturer Part Number: F272-BAG-T
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
24.8.18
Table 79.
170/182
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
Symbol
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
CLKOUT and READY
V
CLKOUT and READY timings
1. These timings are given for characterization purposes only, in order to assure recognition at a specific
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
DD
clock edge.
This adds even more time for deactivating READY. 2t
to the current bus cycle.
= 5V ± 10%, V
2
Parameter
1
1
SS
= 0V, T
A
– 2 + t
= -40 to + 125°C, CL = 50pF
min.
25
10
17
35
17
9
–
–
2
2
0
F
TCL = 12.5 ns
CPU
A
= 40 MHz
2t
A
8 + t
max.
+ t
A
25
–
4
4
–
–
–
–
–
–
and t
C
A
+ t
C
F
refer to the next following bus cycle, t
2TCL + 10
TCL – 3.5
TCL – 2.5
– 2 + t
2TCL
1/2 TCL = 1 to 64MHz
min.
Variable CPU Clock
17
17
–
–
2
2
0
A
ST10F272B/ST10F272E
2t
A
2TCL
8 + t
max.
+ t
–
4
4
–
–
–
–
–
–
C
A
+ t
F
F
refers
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns