ST10F269-DPR STMicroelectronics, ST10F269-DPR Datasheet - Page 94
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ST10F269-DPR
Manufacturer Part Number
ST10F269-DPR
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F269DTR3.pdf
(160 pages)
Specifications of ST10F269-DPR
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F269-DPR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F269
Synchronous Mode Baud Rates
For synchronous operation, the Baud rate
generator provides a clock with 4 times the rate of
the established Baud rate. The Baud rate for
synchronous operation of serial channel ASC0
can be determined by the following formula:
(S0BRL) represents the content of the reload
register, taken as unsigned 13-bit integers,
(S0BRS) represents the value of bit S0BRS (‘0’ or
‘1’), taken as integer.
Table 24 : Commonly Used Baud Rates by Reload Value and Deviation Errors
Note: The deviation errors given in the Table 24 are rounded. To avoid deviation errors use a Baud rate
94/160
Baud Rate (Baud)
5 000 000
112 000
56 000
38 400
19 200
9 600
4 800
2 400
1 200
crystal (providing a multiple of the ASC0/SSC sampling frequency)
900
612
S0BRS = ‘0’, f
Deviation Error
+1.5% / -0.8%
+0.3% / -0.8%
+0.2% / -0.6%
+0.2% / -0.2%
+0.2% / -0.0%
+0.1% / -0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
CPU
= 40MHz
Reload Value
1FE8 / 1FE9
002B / 002C
15B2 / 15B3
0000 / 0000
0058 / 0059
0081 / 0082
0103 / 0104
0207 / 0208
0410 / 0411
0822 / 0823
1045 / 1046
(hexa)
Baud Rate (Baud)
Using the above equation, the maximum Baud
rate can be calculated for any clock speed as
given in Table 24.
3 333 333
B
112 000
S0BRL = (
56 000
38 400
19 200
Sync
9 600
4 800
2 400
1 200
600
407
=
S0BRS = ‘1’, f
4 x [2 + (S0BRS)] x [(S0BRL) + 1]
4 x [2 + (S0BRS)] x B
Deviation Error
+2.6% / -0.8%
+0.9% / -0.8%
+0.9% / -0.2%
+0.4% / -0.2%
+0.1% / -0.2%
+0.1% / -0.1%
+0.1% / -0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
0.0% / 0.0%
CPU
f
CPU
f
CPU
= 40MHz
Reload Value
00AC / 00AD
0AD8 / 0AD9
1FFD / 1FFE
001C / 001D
003A / 003B
015A / 015B
02B5 / 02B6
056B / 056C
15B2 / 15B3
0000 / 0000
0055 / 0056
Sync
(hexa)
) - 1
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