ST10F276-6QR3 STMicroelectronics, ST10F276-6QR3 Datasheet - Page 60
ST10F276-6QR3
Manufacturer Part Number
ST10F276-6QR3
Description
MCU 16BIT 832K FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F276-4TR3.pdf
(231 pages)
Specifications of ST10F276-6QR3
Core Processor
ST10
Core Size
16-Bit
Speed
64MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bootstrap loader
5.4.3
5.4.4
60/231
ST10 configuration in CAN BSL
When the ST10F276E enters BSL mode via CAN, the configuration shown in
automatically set (values that deviate from the normal reset values are marked in bold).
Table 31.
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276E
can return the identification frame. Even if the internal IFLASH is enabled, a code cannot be
executed from it.
Loading the start-up code via CAN
After sending the acknowledge byte, the BSL enters a loop to receive 128 bytes via CAN1.
Hint: The number of bytes loaded when booting via the CAN interface has been extended to
128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings
(synchronization window, ...). This can be achieved by the following sequence of
instructions:
ReconfigureBaud rate:
These 128 bytes are stored sequentially into locations 00’FA40
IRAM, allowing up to 64 instructions to be placed into the RAM area. To execute the loaded
code the BSL then jumps to location 00’FA40
bootstrap loading sequence is now terminated; however, the ST10F276E remains in BSL
Watchdog timer
Register SYSCON
Context pointer CP
Register STKUN
Stack pointer SP
Register STKOV
Register BUSCON0
CAN1 Status/Control register 0000
CAN1 Bit timing register
XPERCON
P4.6 / CAN1_TxD
DP4.6
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
MOV R1,#041h
MOV DPP3:0EF00h,R1 ; Put CAN in Init, enable Configuration Change
MOV R1,#01600h
MOV DPP3:0EF06h,R1 ; 1MBaud at Fcpu = 20 MHz
Function or register
ST10 configuration in CAN BSL
Disabled
0404
FA00
FA00
FA40
FC00
acc. to startup
config.
acc. to ‘0’ frame
042D
‘1’
‘1’
H
H
H
H
H
H
H
(2)
Access
(1)
H
, that is, the first loaded instruction. The
XPEN bit set
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
XRAM1-2, XFlash, CAN1 and XMISC enabled
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
H
through 00’FABF
Notes
Table 31
ST10F276E
H
of the
is
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