ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 29

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
5.4.2
Table 7.
Flash control register 0 high (FCR0H)
The Flash control register 0 high (FCR0H) together with the Flash control register 0 low
(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the test-Flash (B0TF). Moreover, the test-Flash block is seen
by the user in bootstrap mode only.
FCR0H (0x08 0002)
Table 8.
WMS SUSP WPG DWPGSER Reserved SPR
Bit Name
Bit Name
15
RW
4
1
15
LOCK
BSY0
WMS
RW
14
Flash registers access locked
When this bit is set, it means that the access to the Flash control registers FCR0H/-
FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read
access to the registers will output invalid data (software trap 009Bh) and any write
access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash: once it is
found low, the rest of FCR0L and all the other Flash registers are accessible by the user
as well.
Note that FER content can be read when LOCK is low, but its content is updated only
when the BSY0 bit is reset.
Bank 0 busy (IFlash)
This bit indicates that a write operation is running on bank 0 (IFlash). It is automatically
set when bit WMS is set. Setting protection operation sets bit BSY0 (since protection
registers are in this block). When this bit is set, every read access to bank 0 will output
invalid data (software trap 009bh), while every write access to the bank will be ignored.
At the end of the write operation or during a program or erase suspend this bit is
automatically reset and the bank returns to read mode. After a program or erase
Resume this bit is automatically set again.
Write mode start
This bit must be set to start every write operation in the Flash module. At the end of the
write operation or during a suspend, this bit is automatically reset. To resume a
suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of
FER is high (the operation is not accepted). It is also forbidden to start a new write
(program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high.
Resetting this bit by software has no effect.
RW
Flash control register 0 low
Flash control register 0 high
13
RW RW
12
11
10
-
9
FCR
RW
8
Function
7
Function
6
5
Reserved
4
Internal Flash memory
-
3
Reset value: 0000h
2
1
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