C8051F334-GMR Silicon Laboratories Inc, C8051F334-GMR Datasheet - Page 47
C8051F334-GMR
Manufacturer Part Number
C8051F334-GMR
Description
IC 8051 MCU 2K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F334-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
C8051F334-GMR
Manufacturer:
ZILLTEK
Quantity:
3 340
Part Number:
C8051F334-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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50
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
AD0EN
R/W
Bit7
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2–0 bits (see below).
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2–0 = 000b
AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by con-
version.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conver-
sion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conver-
sion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conver-
sion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conver-
sion.
11x: Reserved.
AD0TM
R/W
Bit6
SFR Definition 5.6. ADC0CN: ADC0 Control
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
R/W
Bit5
R/W
Bit4
Rev. 1.7
R/W
Bit3
R/W
Bit2
R/W
Bit1
(bit addressable)
R/W
Bit0
SFR Address:
Reset Value
0xE8
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