C8051F332-GMR Silicon Laboratories Inc, C8051F332-GMR Datasheet - Page 55

• Manufacturer Part Number: C8051F332-GMR
• Description: IC 8051 MCU 4K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F332-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• For Use With: 336-1451 - ADAPTER PROGRAM TOOLSTICK F330
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F330/1/2/3/4/5
6.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen-
dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event.
This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling
rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the
IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both
IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0,
Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to
the IDAC input latches, allowing the IDAC output to change to the new value.
6.1.3. Update Output Based on CNVSTR Edge
The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the
external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to
both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The
particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or
both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the
IDAC input latches, allowing the IDAC output to change to the new value.
6.2.
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC
output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are
mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 6.2.
The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default,
the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide
full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 6.1.
58
Input Data Word
D9
IDAC Output Mapping
(D9–D0)
0x3FF
0x000
0x001
0x200
D8
D7
D6
IDA0H
IDA0OMD[1:0] = ‘1x’
1023/1024 x 2 mA
512/1024 x 2 mA
Output Current
1/1024 x 2 mA
Figure 6.2. IDA0 Data Word Mapping
D5
0 mA
D4
D3
D2
Rev. 1.7
IDA0OMD[1:0] = ‘01’
1023/1024 x 1 mA
512/1024 x 1 mA
Output Current
D1
1/1024 x 1 mA
0 mA
D0
IDA0L
IDA0OMD[1:0] = ‘00’
1023/1024 x 0.5 mA
512/1024 x 0.5 mA
1/1024 x 0.5 mA
Output Current
0 mA