C8051F352-GQR Silicon Laboratories Inc, C8051F352-GQR Datasheet - Page 111

• Manufacturer Part Number: C8051F352-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F352-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x16b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Core: 8051
• Processor Series: C8051F3x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 768 B
• Data Rom Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 17
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 8
• Height: 1.4 mm
• Interface Type: I2C, SMBus, SPI, UART
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.5. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “22.1. Timer 0 and Timer 1’ on page 195) select level or
edge sensitive. The table below lists the possible configurations.
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.5).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“18.1. Priority Crossbar Decoder’ on page 139 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-
sponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac-
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
IT0
1
1
0
0
IN0PL
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
/INT0 Interrupt
Rev. 1.1
IT1
1
1
0
0
IN1PL
C8051F350/1/2/3
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
/INT1 Interrupt
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