C8051F040-GQR Silicon Laboratories Inc, C8051F040-GQR Datasheet - Page 47

• Manufacturer Part Number: C8051F040-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.
The ADC0 subsystem for the C8051F040/1 consists of a 9-channel, configurable analog multiplexer
(AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in
Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under
software control via the Special Function Registers shown in Figure 5.1. The voltage reference used by
ADC0 is selected as described in
C8051F040 devices, or
C8051F041 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power
shutdown when this bit is logic 0.
5.1.
The analog multiplexer can input analog signals to the ADC from four external analog input pins (AIN0.0 -
AIN0.3), Port 3 port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, or
an internally connected on-chip temperature sensor (temperature transfer function is shown in Figure 5.6).
AMUX input pairs can be programmed to operate in either differential or single-ended mode. This allows
the user to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 5.2), the Configuration
register AMX0CF (SFR Definition 5.1), and the Port Pin Selection register AMX0PRT (SFR Definition 5.3).
Table 5.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the
AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-
ration register, ADC0CF (SFR Definition 5.5). The PGA can be software-programmed for gains of 0.5, 2, 4,
8 or 16. Gain defaults to unity on reset.
AGND
12-Bit ADC (ADC0, C8051F040/1 Only)
I/O Pins
Analog
Analog Multiplexer and PGA
Port 3
Input
Input
Pins
HV
SENSOR
TEMP
AMX0CF
ADC0GTH
Figure 5.1. 12-Bit ADC0 Functional Block Diagram
AMUX
(SE or
9-to-1
DIFF)
Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117
AMX0SL
ADC0GTL
X
Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113
+
-
AV+
AD0EN
AGND
ADC0CF
ADC0LTH
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
ADC
12-Bit
AV+
SAR
ADC0CN
ADC0LTL
Start Conversion
12
24
12
Comb.
00
01
10
11
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD0WINT
for
for
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