C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 267
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C8051F130-GQR
Manufacturer Part Number
C8051F130-GQR
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F130-GQR
Manufacturer:
TI
Quantity:
679
Company:
Part Number:
C8051F130-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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19.4.2. Clock Rate Register
Bits7–0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset
R/W
Bit7
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master
mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The
timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation , where SMB0CR is the
unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in
MHz:
The resulting SCL signal high and low times are given by the following equations, where
SYSCLK is the system clock frequency in Hz:
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the
following equation:
R/W
Bit6
SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate
SMB0CR
T
HIGH
R/W
Bit5
T
LOW
T
BFT
4
=
288 0.85
10
R/W
Bit4
4
258 SMB0CR
–
–
256 SMB0CR
4
------------------------------------------------------------- -
Rev. 1.4
–
256 SMB0CR
R/W
Bit3
SYSCLK
--------------------- -
SYSCLK
–
C8051F120/1/2/3/4/5/6/7
4
SYSCLK
R/W
Bit2
1.125
SYSCLK
+
C8051F130/1/2/3
+
1
625ns
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xCF
0
00000000
Reset Value
267
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