HT83C51 Honeywell Microelectronics & Precision Sensors, HT83C51 Datasheet - Page 5

• Manufacturer Part Number: HT83C51
• Description: IC MICROCONTROLLER 8K 40-DIP
• Manufacturer: Honeywell Microelectronics & Precision Sensors
• Series: HTMOS™r

Specifications of HT83C51

• Core Processor: MCS 51
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: Mask ROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -55°C ~ 225°C
• Package / Case: 40-CDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

SERIAL PORT
INTERRUPTS
PCA COUNTER /TIMER
RESET
The Programmable Counter Array (PCA) contains a single
16-bit counter/timer made up of the CL and CH registers.
This timer is used by all 5 capture/compare modules. Its
clock input can be programmed to be from one of four
sources. These are the oscillator frequency divided by 12,
the oscillator frequency divided by 4, Timer 0 overflow, and
an external clock input, ECI, on the alternate function of
port pin P1.2.
The serial port has physically separate receive and transmit
buffers, automatic address recognition and four modes of
operation as shown below.
Mode
There are seven interrupt sources in the HT51. Two are
external interrupts (INT0n, INT1n), three are timer interrupts
(Timer 0, Timer 1, and Timer2), one is a PCA interrupt, and
one is a serial port interrupt as shown below.
The reset input is the RST pin. A reset is accomplished by
holding the RST pin high for a minimum of 4 clock periods
while the clock is running. The CPU generates an internal
reset from the external signal. The port pins are driven to
the reset state 2 oscillator periods after a valid 1 is detected
on the RST pin.
While RST is high, PSENn is pulled high, ALE is pulled low,
and the port pins are pulled weakly high. All SFRs are reset
to their reset values. The internal Data Memory content is
not affected by reset. In addition, if the HT51 is in Idle or
Power Down mode prior to activation of RST, the HT51 will
be taken out of Idle or Power Down mode by the reset.
The processor will begin operation on the second machine
cycle after the RST line is brought low. A memory access
0
1
2
3
PCA interrupt enable
Timer 2 interrupt enable
Serial port interrupt enable
Timer 1 interrupt enable
External interrupt 1 enable
Timer 0 interrupt enable
External interrupt 0 enable
Description
8-bit shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
1/12 times oscillator freq.
variable
1/64 or 1/32 times oscillator freq.
variable
5
INSTRUCTION SET
will be made immediately after the RST line is brought low,
but the data is not brought into the processor. The memory
access will be repeated on the next machine cycle and
actual processing will begin at that time.
The instruction set for the HT51 is compatible to the Intel
MCS-51 instruction set used on the 8XC51FC.
AC CHARACTERISTICS
The AC characteristics for the HT51 are shown in the
following tables. Each of the timing symbols has 5 charac-
ters. The first character is always a ‘T’ (Time). The other
characters, depending on their positions, stand for the
logical name of a signal or the logical status of that signal.
The following is a list of the characters and what they stand for:
A: Address
C: Clock
D: Data
H: Logic level HIGH
I: Instruction
L: Logic level LOW, or ALE
level
P: PSENn
For example, TAVLL = Time from address valid to ALE
low. The characteristics given are over the operating
conditions T
The load capacitance on Port 0, ALE and PSENn = 100
pF. Load capacitance for all other outputs = 50 pF. Inputs
during AC testing are to be driven at V
and 0.45 V for logic 0. Timing measurements are to be
made at V
timing purposes, a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded V
occurs. Timing diagrams are shown to illustrate the signal
relationships depicted in the tables.
(program memory contents)
IH
A
min for logic 1 and V
= -55 C to +225 C, V
DD =
IL
max for logic 0. For
5V 10 %, V
Q: OutputData
R: RDn signal
T: Time
V: Valid
W: WRn signal
X: No longer a
Z: Float
DD
HT83C51
- 0.5V for logic 1
valid logic
OL
/V
OH
SS
= 0V.
level