PIC16C84-04I/SO Microchip Technology, PIC16C84-04I/SO Datasheet - Page 21

• Manufacturer Part Number: PIC16C84-04I/SO
• Description: IC MIC CTL EEPM 1K 4MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

5.2
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
FIGURE 5-3:
output driver in a hi-impedance mode. A '0' on any bit
OR’ed
change interrupt.
Set RBIF
Data bus
WR TRIS
WR Port
RBPU
1997 Microchip Technology Inc.
Note 1: TRISB = '1' enables weak pull-up
(1)
2: I/O pins have diode protection to V
together
PORTB and TRISB Registers
From other
RB7:RB4 pins
(if RBPU = '0' in the OPTION_REG register).
BLOCK DIAGRAM OF PINS
RB7:RB4
Data Latch
TRIS Latch
RD TRIS
RD Port
to
D
D
CK
CK
generate
Q
Q
Q
Q
Latch
DD
the
EN
EN
D
D
and V
RD Port
RB
SS
V
P
DD
.
weak
pull-up
TTL
Input
Buffer
pin
port
I/O
(2)
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-4:
Data bus
RBPU
WR TRIS
WR Port
RB0/INT
Note 1: TRISB = '1' enables weak pull-up
Note 1: If a change on the I/O pin should occur
Read (or write) PORTB. This will end the mis-
match condition.
Clear flag bit RBIF.
(1)
2: I/O pins have diode protection to V
(if RBPU = '0' in the OPTION_REG register).
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not be set.
BLOCK DIAGRAM OF PINS
RB3:RB0
Data Latch
TRIS Latch
RD TRIS
RD Port
D
D
CK
CK
Q
Q
PIC16C84
Q
DD
DS30445C-page 21
EN
and V
D
SS
V
.
P
RD Port
DD
weak
pull-up
TTL
Input
Buffer
pin
I/O
(2)