PIC16C62A/JW Microchip Technology, PIC16C62A/JW Datasheet - Page 110
![IC MCU EPROM 2KX14 PWM 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC16C62A/JW
Manufacturer Part Number
PIC16C62A/JW
Description
IC MCU EPROM 2KX14 PWM 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C62A-04SP.pdf
(8 pages)
Specifications of PIC16C62A/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
EPROM, UV
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C62A/JW
Manufacturer:
MICROCHIP
Quantity:
330
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C62A-04SP PDF datasheet #4
- Current page: 110 of 337
- Download datasheet (3Mb)
PIC16C6X
12.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
FIGURE 12-3: RX PIN SAMPLING SCHEME (BRGH = 0) PIC16C63/R63/65/65A/R65)
FIGURE 12-4: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65)
FIGURE 12-5: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65)
DS30234D-page 110
RC7/RX/DT pin
Q2, Q4 clk
(RC7/RX/DT pin)
baud clk
x4 clk
SAMPLING
baud CLK
x16 CLK
RC7/RX/DT pin
RX
Q2, Q4 clk
baud clk
x4 clk
1
2
First falling edge after RX pin goes low
3
1
4
1
Start Bit
Samples
First falling edge after RX pin goes low
5
2
6
Second rising edge
3
Samples
7
Samples
4
Start Bit
8
2
1
Samples
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
Second rising edge
9
Start bit
bit0
10
Baud clk for all but start bit
2
11
3
Baud CLK for all but start bit
12
4
3
13
1
Samples
14
bit1
1997 Microchip Technology Inc.
2
15
16
1
4
2
Bit0
3
bit0
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