PIC16C73A/JW Microchip Technology, PIC16C73A/JW Datasheet - Page 62
PIC16C73A/JW
Manufacturer Part Number
PIC16C73A/JW
Description
IC MCU EPROM4KX14 A/D PWM 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C72-04SO.pdf
(289 pages)
4.PIC16C73A-20SP.pdf
(8 pages)
Specifications of PIC16C73A/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
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- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C72-04SO PDF datasheet #3
- PIC16C73A-20SP PDF datasheet #4
- Current page: 62 of 289
- Download datasheet (3Mb)
PIC16C7X
7.3
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
FIGURE 7-6:
DS30390E-page 62
RA4/T0CKI
CLKOUT (=Fosc/4)
WDT Enable bit
pin
Watchdog
Timer
Prescaler
Applicable Devices
72 73 73A 74 74A 76 77
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0SE
0
1
PSA
M
U
X
0
1
T0CS
M
U
X
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
1
0
1
PSA
M
U
X
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The pres-
caler is not readable or writable.
Note:
PSA
PS2:PS0
1,x....etc.) will clear the prescaler. When
Cycles
SYNC
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
2
1997 Microchip Technology Inc.
TMR0 reg
Data Bus
8
Set flag bit T0IF
on Overflow
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