PIC17C44/JW Microchip Technology, PIC17C44/JW Datasheet

IC MCU EPROM 8KX16 PWM 40CDIP

PIC17C44/JW

Manufacturer Part Number
PIC17C44/JW
Description
IC MCU EPROM 8KX16 PWM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf (8 pages)
2.PIC17C42A-16P.pdf (241 pages)
3.PIC17C44-16L.pdf (4 pages)

Specifications of PIC17C44/JW

Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
EPROM, UV
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
For Use With
DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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The PIC17C44 (Rev. A) parts you have received con-
form functionally to the PIC17C4X preliminary data
sheet (DS30412 C ), except for the following clarifica-
tions and corrections.
October, 1997 Microchip Technology Inc.
Note:
NONE
As with any windowed EPROM device, please cover the window at all times, except when erasing.
PIC17C44 Rev. A Silicon Errata Sheet
Clarifications/Corrections to the Data Sheet:
The PIC17C44 Preliminary Data Sheet (document
DS30412 C ) that you have received, requires the follow-
ing clarifications and corrections.
1.
2.
3.
The clearing of any interrupt enable bit(s) in the
INTSTA register should be preceded by the dis-
abling of the global interrupt control bit (setting
GLINTD). Global interrupts may then be re-
enabled. The individual interrupts may be re-
enabled without further control of the GLINTD
bit.
When global interrupts are enabled, if the interrupt
flag is being set when the corresponding enable bit
is being cleared the device will branch to the reset
vector address (0h). The interrupt flag will not be
(automatically) cleared.
The RETURN instruction causes an update of the
PCLATH register. The PCLATH register is
loaded with the high address of the RETURN
instruction.
The Table write to internal program memory (self
programming) can occur even when the MCLR
pin is either at the V
When the MCLR pin is at V
sequence occurs, but the programming voltage
is marginal since the MCLR pin is not at the cor-
rect level. This table write may cause the speci-
fied program memory location to be corrupted
(depending on the data in the TABLAT register).
PIC17C44
IH
DS30412C/44/E1A2-page 1
or V
IH
IHH
, the table write
voltage level.

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PIC17C44/JW Summary of contents

Page 1

... NONE Note: As with any windowed EPROM device, please cover the window at all times, except when erasing. October, 1997 Microchip Technology Inc. PIC17C44 Clarifications/Corrections to the Data Sheet: The PIC17C44 Preliminary Data Sheet (document DS30412 C ) that you have received, requires the follow- ing clarifi ...

Page 2

... Table 1. The speci- fication of 5 devices. Ext Bus -:- fn2:fn1 X1:X0 -:- fn5:fn1 Tested Data Sheet Min Typ Max Min Typ — < — < 1 — < — < remains for the PIC17 LC 44 Units Condition Max 5 A PIC17 PIC17 LC 44 October, 1997 Microchip Technology Inc. ...

Page 3

... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...

Page 4

... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 ...

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