PIC16C74B/JW Microchip Technology, PIC16C74B/JW Datasheet - Page 34
![IC MCU EPROM4KX14 A/D PWM 40CDIP](/photos/6/63/66338/150-40-cdip_sml.jpg)
PIC16C74B/JW
Manufacturer Part Number
PIC16C74B/JW
Description
IC MCU EPROM4KX14 A/D PWM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
5.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C74B/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16C74B/JWR
PIC16C74B/JWR
PIC16C74B/JWR
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C63A-04SP PDF datasheet #3
- PIC16C63A-04SP PDF datasheet #4
- PIC16C63A-04SP PDF datasheet #5
- Current page: 34 of 184
- Download datasheet (3Mb)
PIC16C63A/65B/73B/74B
5.4
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
TABLE 5-7:
TABLE 5-8:
DS30605C-page 34
Name
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Legend:
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
Address
08h
88h
89h
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
Note:
PORTD and TRISD Registers
ST = Schmitt Trigger input, TTL = TTL input
PORTD
TRISD
TRISE
The PIC16C63A and PIC16C73B do not
provide PORTD. The PORTD and TRISD
registers are not implemented.
Name
Bit#
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
PORTD FUNCTIONS
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
PORTD Data Direction register
Bit 7
RD7
IBF
Bit 6
RD6
OBF
Buffer Type
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
IBOV
Bit 5
RD5
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PSPMODE
Bit 4
RD4
Function
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
Bit 3
RD3
—
PORTE Data Direction bits
FIGURE 5-6:
Bit 2
RD2
Note 1: I/O pins have protection diodes to V
WR
TRIS
Data
Bus
WR
Port
RD Port
Bit 1
RD1
Data Latch
TRIS Latch
D
D
CK
CK
RD TRIS
Q
Bit 0
RD0
Q
PORTD BLOCK DIAGRAM
2000 Microchip Technology Inc.
Q
xxxx xxxx
1111 1111
0000 -111
Value on:
POR,
EN
BOR
Schmitt
Trigger
Input
Buffer
EN
D
DD
uuuu uuuu
1111 1111
0000 -111
Value on
I/O pin
RESETS
all other
and V
(1)
SS
.
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