AT90S1200-12YI Atmel, AT90S1200-12YI Datasheet - Page 64
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AT90S1200-12YI
Manufacturer Part Number
AT90S1200-12YI
Description
IC MCU 1K FLSH 12MHZ IT 20SSOP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheet
1.AT90S1200-12PC.pdf
(71 pages)
Specifications of AT90S1200-12YI
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
SPI
Peripherals
POR, WDT
Number Of I /o
15
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Ram Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90S1200-12YI
Manufacturer:
ATMEL
Quantity:
5 510
Part Number:
AT90S1200-12YI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Instruction Set Summary (Continued)
64
Mnemonic
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
AT90S1200
Operands
P, b
P, b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Description
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left through Carry
Rotate Right through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit Load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Operation
I/O(P,b)
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0)
Rd(7)
Rd(n)
Rd(3..0)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
1
0
Rr(b)
1
0
1
1
0
1
1
0
0
1
0
0
1
0
←
←
←
←
←
←
←
←
Rd(n+1), Rd(7)
C,Rd(n+1)
C,Rd(n)
Rd(n+1), n = 0..6
←
T
←
←
1
0
Rd(n), Rd(0)
Rd(7..4),Rd(7..4)
1
0
←
←
Rd(n+1),C
Rd(n),C
←
←
0
0
←
←
←
Rd(3..0)
Rd(7)
Rd(0)
Flags
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
0838H–AVR–03/02
# Clocks
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1