AT90S8515A-4JC Atmel, AT90S8515A-4JC Datasheet - Page 61
![IC MCU 8K FLSH 4MHZ LV 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT90S8515A-4JC
Manufacturer Part Number
AT90S8515A-4JC
Description
IC MCU 8K FLSH 4MHZ LV 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheets
1.AT90S8515-4AC.pdf
(112 pages)
2.AT90S8515-4AC.pdf
(4 pages)
3.AT90S8515-4AC.pdf
(4 pages)
Specifications of AT90S8515A-4JC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
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- Download datasheet (3Mb)
0841G–09/01
Default, the external SRAM access, is a 3-cycle scheme as depicted in Figure 43. When
one extra wait state is needed in the access cycle, set the SRW bit (one) in the MCUCR
register. The resulting access scheme is shown in Figure 44. In both cases, note that
PORTA is data bus in one cycle only. As soon as the data access finishes, PORTA
becomes a low-order address bus again.
For details of the timing for the SRAM interface, please refer to Figure 68, Table 37,
Table 38, Table 39 and Table 40, beginning on page 92. Refer to “Architectural Over-
view” on page 7 for a description of the memory map, including address space for
SRAM.
Figure 42. External SRAM Connected to the AVR
Figure 43. External Data SRAM Memory Cycles without Wait State
Data/Address [7..0]
Data/Address [7..0]
System Clock Ø
Address [15..8]
AVR
Port C
Port A
ALE
WR
RD
ALE
WR
RD
Prev. Address
Prev. Address
Prev. Address
T1
Address
Address
D
G
T2
Q
Data
Address
Data
T3
AT90S8515
D[7:0]
A[15:8]
A[7:0]
RD
WR
Address
Address
SRAM
61
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