PIC16C662-04I/PT Microchip Technology, PIC16C662-04I/PT Datasheet - Page 69

• Manufacturer Part Number: PIC16C662-04I/PT
• Description: IC MCU OTP 4KX14 COMP 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C662-04I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

9.7
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external com-
ponents. The block diagram is shown in Figure 9-17.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. This means that the WDT will
run, even if the clock on the OSC1 and OSC2 pins has
been stopped, for example, by execution of a
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT time-out causes the device to wake-up
and continue with normal operation, this is known as a
WDT wake-up. The WDT can be permanently disabled
by clearing configuration bit WDTE (Section 9.1).
9.7.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out period varies with temper-
ature, V
DC specs). If longer time-outs are desired, a prescaler
with a division ratio of up to 1:128 can be assigned to
FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for details of the operation of these bits.
1996 Microchip Technology Inc.
Note: PSA and PS2:PS0 are bits in the OPTION register.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
Name
Config. bits
OPTION
WDT Timer
Enable Bit
MPEEN
RBPU
WDT
Bit 7
From TMR0 Clock Source
(Figure 7-6)
BODEN
INTEDG
Bit 6
SLEEP
(1)
Preliminary
0
1
PIC16C64X & PIC16C66X
PSA
T0CS
M
U
X
Bit 5
CP1
the WDT, under software control, by writing to the
OPTION register. Thus, time-out periods of up to 2.3
seconds can be realized.
The
the postscaler (if assigned to the WDT) and prevent it
from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out (WDT Reset and WDT
wake-up).
9.7.2
It should also be taken in account that under worst case
conditions (V
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
T0SE
Bit 4
CP0
Note:
CLRWDT
0
Time-out
WDT PROGRAMMING CONSIDERATIONS
8 - to - 1 MUX
MUX
PWRTE
WDT
Postscaler
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, other-
wise a WDT reset may occur.
Bit 3
PSA
and
DD
1
SLEEP
8
= Min., Temperature = Max., max.
(1)
instructions clear the WDT and
WDTE
PSA
To TMR0 (Figure 7-6)
Bit 2
PS2
PS2:PS0
FOSC1
Bit 1
PS1
DS30559A-page 69
FOSC0
Bit 0
PS0