PIC16C712/JW Microchip Technology, PIC16C712/JW Datasheet - Page 14
![IC MCU EPROM1KX14 A/D PWM 18CDIP](/photos/12/13/121351/150-18-cdip_sml.jpg)
PIC16C712/JW
Manufacturer Part Number
PIC16C712/JW
Description
IC MCU EPROM1KX14 A/D PWM 18CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C712/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
EPROM, UV
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
PIC16C712/716
TABLE 2-1:
DS41106B-page 12
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’,
Note 1: These registers can be addressed from either bank.
80h
81h
82h
83h
84h
85h
86h
87h
88h-89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-91h
92h
93h-9Eh
9Fh
Addr
Bank 1
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
Shaded locations are unimplemented, read as ‘0’.
are transferred to the upper byte of the program counter.
INDF
OPTION_
REG
PCL
STATUS
FSR
TRISA
TRISB
TRISCCP
PCLATH
INTCON
PIE1
PCON
PR2
ADCON1
Name
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1,2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
RBPU
IRP
Bit 7
—
GIE
—
—
—
—
—
(7)
(4)
INTEDG
RP1
Bit 6
PEIE
ADIE
—
—
—
—
—
(7)
(4)
Bit 5
T0CS
T0IE
RP0
—
—
—
—
—
—
(7)
(7)
PORTA Data Direction Register
Write Buffer for the upper 5 bits of the Program Counter
T0SE
Bit 4
INTE
—
TO
—
—
—
(7)
Bit 3
RBIE
PSA
—
PD
—
—
—
(7)
CCP1IE
PCFG2
TCCP
Bit 2
T0IF
PS2
—
Z
TMR2IE
PCFG1
Bit 1
INTF
POR
PS1
—
DC
(7)
© 2005 Microchip Technology Inc.
TMR1IE
PCFG0
TT1CK
Bit 0
RBIF
BOR
PS0
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--x1 1111 --x1 1111
1111 1111 1111 1111
xxxx x1x1 xxxx x1x1
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- -000 -0-- -000
---- --qq ---- --uu
1111 1111 1111 1111
---- -000
Value on:
POR,
BOR
—
—
—
—
Resets (4)
---- -000
Value on
all other
—
—
—
—