PIC16F84AT-04I/SS Microchip Technology, PIC16F84AT-04I/SS Datasheet - Page 307
![IC MCU FLASH 1KX14 EE 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84AT-04I/SS
Manufacturer Part Number
PIC16F84AT-04I/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-04I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
- Current page: 307 of 688
- Download datasheet (3Mb)
17.4.8
1997 Microchip Technology Inc.
Baud Rate Generator
In I
register
stops until another reload has taken place. In I
cally. If Clock Arbitration is taking place for instance, the BRG will be reloaded when the SCL pin
is sampled high
Figure 17-18: Baud Rate Generator Block Diagram
Figure 17-19: Baud Rate Generator Timing With Clock Arbitration
2
SDA
SCL
BRG
value
BRG
reload
C master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD
(Figure
SSPM3:SSPM0
17-18). When the BRG is loaded with this value, the BRG counts down to 0 and
(Figure
BRG counts
down
03h
SCL
17-19).
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
SSPM3:SSPM0
Preliminary
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG counts
down
Reload
Control
CLKOUT
01h
2
C master mode, the BRG is reloaded automati-
Reload
Section 17. MSSP
BRG counts
down
00h (hold off)
BRG Down Counter
DX-1
SSPADD<6:0>
SCL allowed to transition high
03h
DS31017A-page 17-31
Fosc/4
02h
17
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