PIC16LC773T/SO Microchip Technology, PIC16LC773T/SO Datasheet - Page 93
![IC MCU OTP 4KX14 A/D PWM 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16LC773T/SO
Manufacturer Part Number
PIC16LC773T/SO
Description
IC MCU OTP 4KX14 A/D PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC773T/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8.2.18.16 BUS COLLISION DURING A REPEATED
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0.
asserted, and when sampled high, the SDA pin is sam-
pled. If SDA is low, a bus collision has occurred (i.e.
another master is attempting to transmit a data ’0’). If
FIGURE 8-38: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 8-39: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
1999 Microchip Technology Inc.
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
START CONDITION
’0’
’0’
’0’
’0’
The SCL pin is then de-
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
Advance Information
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
however SDA is sampled high then the BRG is
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
If at the end of the BRG time out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is com-
plete
(Figure
8-38).
T
Cleared in software
BRG
PIC16C77X
Interrupt cleared
in software
’0’
’0’
DS30275A-page 93
’0’
’0’
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