PIC17C43-25I/PT Microchip Technology, PIC17C43-25I/PT Datasheet - Page 103

• Manufacturer Part Number: PIC17C43-25I/PT
• Description: IC MCU OTP 4KX16 PWM 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-25I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC164315 - MODULE SKT MPLAB PM3 44TQFP309-1008 - ADAPTER 44-TQFP TO 40-DIPAC174005 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

14.3
The Watchdog Timer’s function is to recover from soft-
ware malfunction. The WDT uses an internal free run-
ning on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and OSC2/CLK-
OUT pins of the device has been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out gener-
ates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as ' 00 ' (Section 14.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
14.3.1
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temper-
ature, V
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
1996 Microchip Technology Inc.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
14.3.2
The WDT and postscaler are cleared when:
• The device is in the reset state
• A SLEEP instruction is executed
• A CLRWDT instruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
14.3.3
It should also be taken in account that under worst case
conditions (V
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
14.3.4
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 T
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. When in sleep, the WDT
does not increment.
CLEARING THE WDT AND POSTSCALER
WDT PROGRAMMING CONSIDERATIONS
WDT AS NORMAL TIMER
DD
= Min., Temperature = Max., max.
OSC
cycles. On overflow, the TO bit
PIC17C4X
DS30412C-page 103