AT89S53-24AI Atmel, AT89S53-24AI Datasheet - Page 15
![IC MICRO CTRL 24MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
AT89S53-24AI
Manufacturer Part Number
AT89S53-24AI
Description
IC MICRO CTRL 24MHZ 44TQFP
Manufacturer
Atmel
Series
89Sr
Datasheet
1.AT89S53-24JI.pdf
(35 pages)
Specifications of AT89S53-24AI
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
3 x 16 bit
Operating Supply Voltage
4 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89S53-24AI
Manufacturer:
HIROSE
Quantity:
101
Part Number:
AT89S53-24AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
UART
The UART in the AT89S53 operates the same way as the
UART in the AT89C51, AT89C52 and AT89C55. For fur-
ther information, see the October 1995 Microcontroller
Data Book, page 2-49, section titled, “Serial Interface.”
Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the AT89S53 and
peripheral devices or between several AT89S53 devices.
The AT89S53 SPI features include the following:
• Full-duplex, 3-wire Synchronous Data Transfer
• Master or Slave Operation
• 1.5 MHz Bit Frequency (max.)
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End of Transmission Interrupt Flag
Figure 7. SPI Master-slave Interconnection
Figure 8. SPI transfer Format with CPHA = 0
*Not defined but normally MSB of character just received
0787E–MICRO–3/06
CLOCK GENERATOR
SPI
MSB
8-BIT SHIFT REGISTER
MASTER
LSB
MISO
MOSI MOSI
SCK
SS
V
• Write Collision Flag Protection
• Wakeup from Idle Mode (Slave Mode Only)
The interconnection between master and slave CPUs with
SPI is shown in the following figure. The SCK pin is the
clock output in the master mode but is the clock input in the
slave mode. Writing to the SPI data register of the master
CPU starts the SPI clock generator, and the data written
shifts out of the MOSI pin and into the MOSI pin of the
slave CPU. After shifting one byte, the SPI clock generator
stops, setting the end of transmission flag (SPIF). If both
the SPI interrupt enable bit (SPIE) and the serial port inter-
rupt enable bit (ES) are set, an interrupt is requested.
The Slave Select input, SS/P1.4, is set low to select an
individual SPI device as a slave. When SS/P1.4 is set high,
the SPI port is deactivated and the MOSI/P1.5 pin can be
used as an input.
There are four combinations of SCK phase and polarity
with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are
shown in Figure 8 and Figure 9.
CC
MISO
SCK
SS
MSB
8-BIT SHIFT REGISTER
SLAVE
LSB
AT89S53
15