ATTINY12-8PI Atmel, ATTINY12-8PI Datasheet
ATTINY12-8PI
Specifications of ATTINY12-8PI
Related parts for ATTINY12-8PI
ATTINY12-8PI Summary of contents
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... Nonvolatile Program and Data Memory – 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) – 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security • ...
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... Flash EEPROM ATtiny11L 1K - ATtiny11 1K - ATtiny12V ATtiny12L ATtiny12 The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Register Voltage Range Frequency 32 2.7 - 5.5V 0-2 MHz 32 4.0 - 5.5V 0-6 MHz 32 1 ...
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... The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. ...
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... ATtiny12 Block Diagram ATtiny11/12 4 Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM six general-purpose I/O lines, 32 general-purpose working regis- ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con- tinue functioning ...
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... Ground pin. Port 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below ...
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Register Summary ATtiny11 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 ...
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... Register Summary ATtiny12 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 - $32 TCNT0 Timer/Counter0 (8 Bit) $31 OSCCAL Oscillator Calibration Register $30 Reserved ... Reserved $22 Reserved $21 WDTCR - $20 Reserved $1F Reserved $1E EEAR - $1D EEDR EEPROM Data Register $1C EECR - $1B Reserved ...
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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr ...
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Instruction Set Summary (Continued) Mnemonics Operands Description DATA TRANSFER INSTRUCTIONS LD Rd,Z Load Register Indirect ST Z,Rr Store Register Indirect MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate IN Rd Port OUT P, Rr Out ...
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Ordering Information ATtiny11 Power Supply Speed (MHz) 2.7 - 5.5V 2 4.0 - 5.5V 6 Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil- lator has ...
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... Ordering Code ATtiny12V-1PC ATtiny12V-1SC ATtiny12V-1PI (2) ATtiny12V-1PU ATtiny12V-1SI (2) ATtiny12V-1SU ATtiny12L-4PC ATtiny12L-4SC ATtiny12L-4PI 4 (2) ATtiny12L-4PU ATtiny12L-4SI (2) ATtiny12L-4SU ATtiny12-8PC ATtiny12-8SC ATtiny12-8PI 8 (2) ATtiny12-8PU ATtiny12-8SI (2) ATtiny12-8SU Package Type ATtiny11/12 Package Operation Range 8P3 Commercial (0°C to 70°C) 8S2 8P3 8P3 Industrial (-40°C to 85°C) 8S2 ...
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Packaging Information 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the ...
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Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included recommended that upper ...
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... Updated chapter layout. 2. Updated Power-down in “Sleep Modes for the ATtiny11” on page 20. 3. Updated Power-down in “Sleep Modes for the ATtiny12” on page 20. 4. Updated Table 16 on page 36. 5. Updated “Calibration Byte in ATtiny12” on page 49. ...
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