ATMEGA128L-8AI Atmel, ATMEGA128L-8AI Datasheet - Page 282
![IC AVR MCU 128K 8MHZ LV 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128L-8AI
Manufacturer Part Number
ATMEGA128L-8AI
Description
IC AVR MCU 128K 8MHZ LV 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128L-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA128L8AI
Available stocks
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Preventing Flash
Corruption
Programming Time for
Flash when Using
SPM
Simple Assembly
Code Example for a
Boot Loader
282
ATmega128
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
low for the CPU and the Flash to operate properly. These issues are the same as for board level
systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
3. Keep the AVR core in Power-down Sleep mode during periods of low V
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 111. SPM Programming Time.
Flash write (page erase, page write,
and write lock bits by SPM)
bits to prevent any Boot Loader software updates.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
be used. If a Reset occurs while a write operation is in progress, the write operation will
be completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
.equ PAGESIZEB = PAGESIZE*2
.org SMALLBOOTSTART
Write_page:
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during self-programming (page erase and page write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcsrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
; page erase
ldi
call Do_spm
; re-enable the RWW section
ldi
call Do_spm
spmcsrval, (1<<PGERS) | (1<<SPMEN)
spmcsrval, (1<<RWWSRE) | (1<<SPMEN)
Symbol
CC,
the Flash program can be corrupted because the supply voltage is too
Min Programming Time
;PAGESIZEB is page size in BYTES, not words
3.7 ms
CC
Table 111
Max Programming Time
Reset Protection circuit can
4.5 ms
shows the typical pro-
CC
. This will pre-
2467V–AVR–02/11
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