ATMEGA8-16PC Atmel, ATMEGA8-16PC Datasheet - Page 75

• Manufacturer Part Number: ATMEGA8-16PC
• Description: IC AVR MCU 8K 16MHZ COM 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8-16PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA816PC

16-bit
Timer/Counter1
Overview
2486Z–AVR–02/11
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
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Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
actual placement of I/O pins, refer to
ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
True 16-bit Design (that is, allows 16-bit PWM)
Two Independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
“16-bit Timer/Counter Register Description” on page
“Pin Configurations” on page
Figure 32 on page
2. CPU accessible I/O Regis-
ATmega8(L)
96.
76. For the
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