ATMEGA161L-4PC Atmel, ATMEGA161L-4PC Datasheet - Page 52
ATMEGA161L-4PC
Manufacturer Part Number
ATMEGA161L-4PC
Description
IC AVR MCU 16K LV 4MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161L-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Timer/Counter1 Control
Register B – TCCR1B
52
ATmega161(L)
• Bits 1..0
These bits select PWM operation of Timer/Counter1 as specified in Table 15. This mode
is described on page 55.
Table 15. PWM Mode Select
• Bit 7
When the ICNC1 bit is cleared (zero), the Input Capture trigger noise canceler function
is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the
ICP (Input Capture pin) as specified. When the ICNC1 bit is set (one), four successive
samples are measured on the ICP (Input Capture pin), and all samples must be high/low
according to the Input Capture trigger specification in the ICES1 bit. The actual sampling
frequency is XTAL clock frequency.
• Bit 6
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the Input Capture pin (ICP). While
the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Cap-
ture Register (ICR1) on the rising edge of the Input Capture pin (ICP).
• Bits 5, 4
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 3
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-
ues counting and is unaffected by a compare match. When a prescaling of 1 is used and
the Compare A Register is set to C, the timer will count as follows if CTC1 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode,
the Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the
Timer/Counter wraps when it reaches the TOP value. Refer to page 55 for a detailed
description.
Bit
$2E ($4E)
Read/Write
Initial Value
PWM11
0
0
1
1
–
–
–
ICNC1: Input Capture1 Noise Canceler (4 CKs)
ICES1: Input Capture1 Edge Select
CTC1: Clear Timer/Counter1 on Compare Match
–
–
PWM11, PWM10: Pulse Width Modulator Select Bits
ICNC1
Res: Reserved Bits
R/W
7
0
PWM10
0
1
0
1
ICES1
R/W
6
0
Description
PWM operation of Timer/Counter1 is disabled.
Timer/Counter1 is an 8-bit PWM.
Timer/Counter1 is a 9-bit PWM.
Timer/Counter1 is a 10-bit PWM.
R
5
–
0
R
4
–
0
CTC1
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
CS10
R/W
0
0
1228D–AVR–02/07
TCCR1B
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