PIC16C717/JW Microchip Technology, PIC16C717/JW Datasheet - Page 95
![IC MCU EPROM2KX14 A/D PWM 18CDIP](/photos/12/13/121351/150-18-cdip_sml.jpg)
PIC16C717/JW
Manufacturer Part Number
PIC16C717/JW
Description
IC MCU EPROM2KX14 A/D PWM 18CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C770-ISO.pdf
(220 pages)
3.PIC16C770-ISO.pdf
(6 pages)
4.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C717/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
EPROM, UV
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
18-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- PIC16F818-ISO PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16C770-ISO PDF datasheet #4
- Current page: 95 of 220
- Download datasheet (4Mb)
9.2.16
Clock arbitration occurs when the master, during any
receive, transmit or repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
FIGURE 9-22:
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
2002 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
Advance Information
SCL line sampled once every machine cycle (Tosc
Hold off BRG until SCL is sampled high.
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-22).
PIC16C717/770/771
T
BRG
SCL = 1 BRG starts counting
clock high interval.
DS41120B-page 93
4).
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