PIC18C658-E/PT Microchip Technology, PIC18C658-E/PT Datasheet - Page 12
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PIC18C658-E/PT
Manufacturer Part Number
PIC18C658-E/PT
Description
IC MCU OTP 16KX16 CAN 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C658E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18C658/858
6. Module: Interrupts
REGISTER 7-1:
FIGURE 1:
DS80107J-page 12
The operation of the GIE/GIEH bit (INTCON<7>) is
clarified as follows: when the bit is cleared, all
interrupts are disabled. This is regardless of the
state of the IPEN bit (RCON<7>), the priority of the
interrupt, or whether or not the interrupt is
unmasked. This varies from the original descrip-
tion, in which clearing the bit when IPEN = 1 would
only disable high priority interrupts.
The seventh paragraph in Section 7.0 of the
Device Data Sheet (beginning “When an interrupt
is responded to....”) is amended by adding the
following sentence to the end:
Low Priority Interrupt Generation
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
bit 7
TMR1IF
TMR1IE
TMR1IP
XXXXIE
XXXXIP
XXXXIF
INTERRUPT LOGIC (EXCERPT)
INTCON REGISTER (EXCERPT)
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON<7>) = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
Additional Peripheral Interrupts
TMR0IE
TMR0IP
TMR0IF
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
“It is important to note, however, that clearing the
GIE/GIEH bit, regardless of the state of the IPEN
bit, will disable all interrupts.”
The changes to the bit descriptions in Register 7-1
in the Device Data Sheet are shown in the excerpt
below (changes in bold).
Also, the interrupt logic funnel shown in Figure 7-1
of the Device Data Sheet is amended with the
addition of a GIE/GIEH control line, as shown in
Figure 1 (new material in bold line).
2003 Microchip Technology Inc.
GIEL/PEIE
GIE/GEIH
Interrupt to CPU
Vector to Location
0018h