PIC16F84A-20E/SO Microchip Technology, PIC16F84A-20E/SO Datasheet - Page 146
![IC MCU CMOS 20MHZ 1K FLSH 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F84A-20E/SO
Manufacturer Part Number
PIC16F84A-20E/SO
Description
IC MCU CMOS 20MHZ 1K FLSH 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84A-20E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
- Current page: 146 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
9.3
DS31009A-page 9-6
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB.
Setting a bit in the TRISB register puts the corresponding output driver in a high-impedance input
mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected
pin(s).
Example 9-2:
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the
pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automati-
cally turned off when the port pin is configured as an output. The pull-ups are disabled on a
Power-on Reset.
Figure 9-4: Block Diagram of RB3:RB0 Pins
CLRF
CLRF
BSF
MOVLW
MOVWF
Note 1: I/O pins have diode protection to V
STATUS
PORTB
STATUS, RP0
0xCF
TRISB
Initializing PORTB
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear
the RBPU bit (OPTION<7>).
Data bus
WR TRIS
WR Port
To Peripheral Module
RBPU
(2)
; Bank0
; Initialize PORTB by clearing output
;
; Select Bank1
; Value used to initialize data direction
; PORTB<3:0> = inputs, PORTB<5:4> = outputs
;
data latches
PORTB<7:6> = inputs
RD TRIS
RD Port
TRIS Latch
Data Latch
D
D
CK
CK
Schmitt Trigger
Buffer
DD
Q
Q
and V
SS
.
Q
1997 Microchip Technology Inc.
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
weak
pull-up
I/O
pin
(1)
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